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1 8-character, 16-segment, microprocessor compatible, led display decoder driver ICM7245 the ICM7245 is an 8-character, alphanumeric display driver and controller which provides all the circuitry required to interface a microprocessor or di gital system to a 16-segment display with internal pull-up resi stors. it is primarily intended for use in microprocessor sy stems, where it minimizes hardware and software overhead . incorporated on-chip are a 64-character ascli decoder, 8x6 memory, high power character and segment drivers, and the multiplex scan circuitry. 6-bit ascll data to be displayed is written into the memory directly from the microprocessor data bus. data location depends upon the selection of either sequential (mode = 1) or random access mode (mode = 0). in the sequential access mode the first entry is stored in the lowest location and displayed in the ?left-most? character position. each subsequent entry is automatically stored in the next higher location and displayed to the immediate ?right? of the previous entry. a display full signal is provided after 8 entries; this signal can be used for casc ading devices together. a clr pin is provided to clear the memory and reset the location counter. the random access mode allows the processor to select the memory address and display digit for each input word. the character multiplex scan runs whenever data is not being entered. it scans the memory and character drivers, and ensures that the decoding from memory to display is done in the proper sequence. intercharacter blanking is provided to avoid display ghosting. features ? single supply +3.3v operation ? 16-segment fonts with decimal point ? up to 8 character display driver ? has internal pull-up resistors of 136 ? typical ? microprocessor compatible ? directly drives led common cathode displays ? cascadable without additional hardware ? standby feature turns display off; puts chip in low power mode ? sequential entry or random entry of data into display ? character and segment drivers, all mux scan circuitry, 8x6 static memory and 64-charac ter ascll font generator included on-chip ? pb-free (rohs compliant) ordering information part number (note 2) part marking temp. range (c) package (pb-free) pkg. dwg. # ICM7245aim44z ICM7245 aim44z -25c to +85c 44 ld mqfp q44.10x10 ICM7245aim44zt (note 1) ICM7245 aim44z -25c to +85c 44 ld mqfp (tape and reel) q44.10x10 notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ICM7245 . for more information on msl, please see tech brief tb363 . caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. october 29, 2013 fn8587.0
ICM7245 2 fn8587.0 october 29, 2013 pin configuration ICM7245 (16-segment character) (44 ld mqfp) top view d2 d1 d0 seg a2 seg a1 seg d1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 d3 d4 d5 cs nc nc wr 28 27 26 25 24 23 22 21 20 19 18 v ss nc nc char1 osc/off a 2 /disp full a 1 /clr a 0 /sen 39 38 37 36 35 34 33 32 31 30 29 44 43 42 41 40 v dd seg l seg g2 seg b seg i seg f seg d2 dp seg h seg j mode seg c seg k seg g1 seg e seg m char8 char7 char6 char5 char4 char3 char2 pin descriptions signal pin function d0 - d5 4 thru 9 6-bit ascll data input pins (active high). cs 10 chip select from p address decoder, etc. wr 13 write pulse input pin (active low). for an active high write pulse, cs can be used. mode 29 selects data entry mode. high selects sequential access (sa) mode where first entry is displayed in ?leftmost? character and subsequent en tries appear to the ?right?. low selects random access (ra) mode where data is displayed on the charac ter addressed via a0 thru a2 address pins. a0/sen 28 in ra mode it is the lsb of the character address. in sa mode it is used for cascading devices for displays of more than 8 characters (a ctive high enables device controller). a1/clr 27 in ra mode this is the second bit of the address. in sa mode, a low input will clear the serial address counter, the data memory and the display. a2/disp full 26 in ra mode this is the msb of the address. in sa mode, the output goes high after 8 entries, indicating display full. osc/off 25 oscillator input pin. adding capacitance to v dd will lower the internal oscillator frequency. an external oscillator can be applied to this pin. a low at this input sets the device into a (shutdown) mode, shutting off the display and oscillato r but retaining data stored in memory. seg d1, seg a1, seg a2; seg j, seg h, dp, seg d2, seg f, seg i, seg b, seg g2, seg i; seg m, seg e, seg g 1, seg k, seg c 1 thru 3, 30 thru 38 40 thru 44 segment driver outputs. char8 thru char5, char4 thru char2, char1 14 thru 17, 19 thru 21, 24 character driver outputs. v ss 18 supply ground. v dd 39 positive power supply +3.0v to +3.6v. nc 11, 12, 22, 23 no connection.
ICM7245 3 fn8587.0 october 29, 2013 functional block diagram mode a0/sen a1/clr multiplexer sequential character oscillator data input d0 to d5 d q cl data latches 8x6 d1 cl clr d0 adr 6 64x17 rom segment drivers segment one shot 8 17 wr cs mux sel d cl cl d address latches d cl q control cl en clr sequential address counter overflow latch outputs seg x with data memory 8 8 character drivers sel 3 address mulitplexer and decoder inter-character blanking character multiplex counter multiplex oscillator osc/off 3 3 a2/disp full char n character outputs int pull-up resistor of 136 ? typ.
ICM7245 4 fn8587.0 october 29, 2013 absolute maximum rating s thermal information supply voltage v dd - v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5v input voltage (any terminal) . . . . . . . . . . . . . . . . . .v dd + 0.3v to v ss - 0.3v character output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300ma segment output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ma operating conditions t emperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25c to +85c thermal resistance (typical) ja (c/w) jc (c/w) 44 ld mqfp package (notes 4, 5) . . . . . . . 70 21 storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a low effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for jc , the ?case temp? location is taken at the package top center. electrical specifications v dd = 3.3v, v ss = 0v, t a = +25c, unless otherwise specified. parameter symbol test conditions min typ max units dc characteristics supply voltage (v dd - v ss )v supp 33.33.6v operating supply current i dd v supp = 3.6v, 10 segments on, all 8 characters - 50 - ma quiescent supply current i stby v supp = 3.6v, osc/off pin < 0.5v, cs = v ss - 3.2 25 a input high voltage v ih 2.0 - - v input low voltage v il --0.8v input current i in -10 - +10 a character drive current i char v supp = 3.3v, v out = 1v 70 135 - ma v supp = 3.0v, v out = 2v 120 175 235 ma character leakage current i chlk --100a segment drive current i seg v supp = 3.3v, v out = 2v 3.7 5.1 6.7 ma segment leakage current i slk -0.0210a display full output low v ol i ol = 1.6ma - - 0.4 v display full output high v oh l ih = 100a 2.4 - - v display scan rate f ds - 300 - hz electrical specifications drive levels 0.4v and 2.4v, timing measured at 0.8v and 2.0v. v dd = 3.3v, t a = +25c, unless otherwise specified. parameter symbol test conditions min typ max units ac characteristics wr , clear pulse width low t wpi 500 250 - ns wr , clear pulse width high (note 6) t wph - 250 - ns data hold time t dh 0-100 - ns data setup time t ds 250 150 - ns address hold time t ah 125 - - ns address setup time t as 100 - - ns cs setup time t cs 0- -ns pulse transition time t t --100ns sen setup time t sen 0 -25 - ns display full delay t wdf 760 540 - ns
ICM7245 5 fn8587.0 october 29, 2013 capacitance parameter symbol test conditions min typ max units input capacitance c ln (note 7) - 5 - pf output capacitance c o (note 7) - 5 - pf notes: 6. in sequential mode wr high must be t sen +t wdf . 7. for design reference only, not tested. timing waveforms figure 1. random access timing figure 2. sequential access mode timing (mode = 1) cs address write data valid t cs t ah t as t t t dh t t t wc t wpi t whp t ds valid t wph wr clear sen display full char t sen char char t wdf 12 8
ICM7245 6 fn8587.0 october 29, 2013 figure 3. display characters multiplex timing diagram timing waveforms (continued) internal char 1 characters drive signals ~5s ~300s inter-character blanking char 2 char 3 char 4 char 5 char 6 char 7 char 8 inter-character blanking signal
ICM7245 7 fn8587.0 october 29, 2013 test circuit figure 4. d2 d1 d0 seg a2 seg a1 seg d1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 d3 d4 d5 cs nc nc wr 28 27 26 25 24 23 22 21 20 19 18 v ss nc nc char1 osc/off a 2 /disp full a 1 /clr a 0 /sen 39 38 37 36 35 34 33 32 31 30 29 44 43 42 41 40 v dd seg l seg g2 seg b seg i seg f seg d2 dp seg h seg j mode (sa/ra ) seg c seg k seg g1 seg e seg m char8 char7 char6 char5 char4 char3 char2 segments segments segments v dd 17 segments char 8 char 7 char 6 char 5 char 4 char 3 char 2 char 1 display v dd nc (for sa mode) v dd full output
ICM7245 8 fn8587.0 october 29, 2013 typical applications figure 5. driving two rows of characters from a serial input rri drr hd6402 uart rbr1 - rbr6 rbr8 rbr7 dr 6 bit bus +3.3v clr cs sen wr d0 - d5 cs ICM7245 seg disp full char etc. etc. clr cs sen wr d0 - d5 cs ICM7245 seg disp full char cs sen clr char seg ICM7245 cs disp full d0 - d5 cs sen clr char seg ICM7245 cs disp full d0 - d5 wr wr 200pf out v + tr th icl7555 delay 20k +3.3v +3.3v +3.3v 8 characters 8 characters 8 characters 8 characters
ICM7245 9 fn8587.0 october 29, 2013 figure 6. multicharacter display using sequential access mode figure 7a. common cathode display figure 7b. common anode display figure 7. driving large displays typical applications (continued) 8-character led display 8 clr +3.3v sen mode wr d0 - d5 cs char seg disp full v dd v ss data wr cs, first 8 characters second 8 characters nth 8 characters 8-character led display 8-character led display 88 +3.3v clr clr sen mode wr d0 - d5 cs char seg disp full v dd v ss clr sen mode wr d0 - d5 cs char seg disp full v dd v ss +3.3v +3.3v +3.3v +3.3v +3.3v 6 17 6 6 bus (wr) 17 17 +3.3v 136 ? 1ma 2n2219 14 ? (100ma peak ) char 14ma 2n6034 1.4a peak gnd r on = 6 ? ICM7245 +3.3v gnd seg +3.3v 136 ? 2n2219 (100ma peak ) 1.4a peak gnd r on = 6 ? ICM7245 +3.3v gnd seg 300 ? gnd +3.3v 1k 1k 25 ? 1k char 2n6034
ICM7245 10 fn8587.0 october 29, 2013 figure 8. random access 32-character display in a 80c48 system display font and segment assignments figure 9. 16-segment character font with decimal point typical applications (continued) cs a2 a1 a0 d0 - d5 wr cs a2 a1 a0 d0 - d5 wr cs a2 a1 a0 d0 - d5 wr cs a2 a1 a0 d0 - d5 wr 80c35 80c48 wr db5 - db0 db6 db7 p22 p21 p20 6 bit bus ICM7245 ICM7245 ICM7245 ICM7245 8 characters 8 characters 8 characters 8 characters 00 01 d5, d4 1 0 11 d30000000011111111 d20000111100001111 d10011001100110011 d00101010101010101 g1 g2 k ml f e b c a1 hj i a2 d2 d1 dp
ICM7245 11 fn8587.0 october 29, 2013 detailed description w r , cs these pins are immediately functi onally anded, so all actions described as occurring on an edge of wr , with cs enabled, will occur on the equivalent (last) enabling or (first) disabling edge of any of these inputs. the delays from cs pins are slightly (about 5ns) greater than from wr due to the additional inverter required on the former. mode the mode pin input is latched on the falling edge of wr (or its equivalent, see wr description). the location (in data memory) where incoming data will be placed is determined either from the address pins or the sequential address counter. this is controlled by mode input. mode also controls the function of a0/sen, a1/clr , and a2/dlsplay full lines. random access mode when the internal mode latch is set for random access (ra) (mode latched low), the address input on a0, a1 and a2 will be latched by the falling edge of wr (or its equivalent). subsequent changes on the address lines will not affect device operation. this allows use of a multiplexed 6-bit bus controlling both address and data, with timing controlled by wr . sequential access mode if the internal latch is set for sequential access (sa) , (mode latched high), the serial enable input or sen will be latched on the falling edge of wr (or its equivalent). the clr input is asynchronous, and will force-clear the sequential address counter to address 000 (chara cter 1), and set all data memory contents to 100000 (blank) at any time. the display full output will be active in sa mode to indicate the overflow status of the sequential address counter. if this output is low, and sen is (latched) high, the co ntents of the counter will be used to establish the data memory location for the data input. the counter is then incremente d on the rising edge of wr . if sen is low, or display full is high, no action will occur. this allows easy ?daisy-chaining? of display drivers for multiple character displays in a sequential access mode. changing modes care must be exercised in any application involving changing from one mode to another. the change will occur only on a falling edge of wr (or its equi valent). when changing mode from sequential access to random access , note that a2/dlsplay full will be an output until wr has fallen low, and an address drive here could cause a conflict. when changing from random access to sequential access , a1/clr should be high to avoid inadvertent clearing of the data memory and sequential address counter. display full will become active immediately after the rising edge of wr. data entry the input data is latched on the rising edge of wr (or its equivalent) and then stored in the data memory location determined as described above. the six data bits can be multiplexed with the address information on the same lines in random access mode. timing is controlled by the wr input. osc/off the device includes a relaxation oscillator with an internal capacitor and a nominal frequency of 200khz. by adding external capacitance to v dd at the osc/off pin, this frequency can be reduced as far as desired. alternatively, an external signal can be injected on this pin. the oscillator (or external) frequency is pre-divided by 64, and then further divided by 8 in the multiplex counter, to drive the character drive lines (figure 3). an inter-character blanking signal is derived from the pre-divider. an additional comparator on the osc/off input detects a level lower than the relaxation oscillator's range, and blanks th e display, disables the display full output (if active), and clears the pre-divider and multiplex counter. this puts the circuit in a low-power-dissipation mode figure 10. segment and charac ter drivers output circuit display font and segment assignments (continued) v dd segment driver r character driver r ds(on) ~ 7.4 ? v ss char n segment leds seg x display v led = 2v r typical =136 ?
ICM7245 12 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8587.0 october 29, 2013 for additional products, see www.intersil.com/en/products.html in which all outputs are effectively open circuits, except for parasitic diodes to the supply lines. thus a display connected to the output may be driven by another circuit (including another ICM7245) without driver conflicts. display output the output of the multiplex coun ter is decoded and multiplexed into the address input of the data memory, except during wr operations (in sequential access mode, with sen high and display full low), when it scans through the display data. the address decoder also drives the character outputs, except during the inter-character blanki ng interval (nominally about 5s). each character output lasts nominally about 300s, and is repeated nominally every 2.5ms, i.e., at a 400hz rate (times are based on internal oscillator without external capacitor). the 6 bits read from the data memory are decoded in the rom to the 17 segment signals, which drive the segment outputs. both character and segment ou tputs are disabled during wr operations (with sen high and display full low for sequential access mode). the outputs may also be disabled by pulling osc/off low. the decode pattern from 6 bits to 17 segments is done by a rom pattern according to the ascll font shown. custom decode patterns can be arranged, within these limitations, by contacting intersil sales support . about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change october 29, 2013 fn8587.0 initial release
ICM7245 13 fn8587.0 october 29, 2013 metric plastic quad flatpack packages (mqfp) d d1 e e1 -a- pin 1 a2 a1 a 12 o -16 o 12 o -16 o 0 o -7 o 0.40 0.016 min l 0 o min plane b 0.005/0.009 0.13/0.23 with plating base metal seating 0.005/0.007 0.13/0.17 b1 -b- e 0.008 0.20 a-b s d s c m 0.076 0.003 -c- -d- -h- q44.10x10 (jedec ms-022ab issue b) 44 lead metric plastic quad flatpack package symbol inches millimeters notes min max min max a - 0.096 - 2.45 - a1 0.004 0.010 0.10 0.25 - a2 0.077 0.083 1.95 2.10 - b 0.012 0.018 0.30 0.45 6 b1 0.012 0.016 0.30 0.40 - d 0.515 0.524 13.08 13.32 3 d1 0.389 0.399 9.88 10.12 4, 5 e 0.516 0.523 13.10 13.30 3 e1 0.390 0.398 9.90 10.10 4, 5 l 0.029 0.040 0.73 1.03 - n44 447 e 0.032 bsc 0.80 bsc - rev. 2 4/99 notes: 1. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 2. all dimensions and toleranc es per ansi y14.5m-1982. 3. dimensions d and e to be determined at seating plane . 4. dimensions d1 and e1 to be determined at datum plane . 5. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm (0.010 inch) per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. ?n? is the number of terminal positions. -c- -h-

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